I said “1000 times” when a GS interviewer asked for an estimate of relative latency of main memory vs register. He said that’s about right.
Numbers below were taken from the CPU Cache Flushing Fallacy blog post, which indicates that for a particular 2012-era Intel processor, the following is true:
- register access = 4 instructions per cycle
- L1 latency = 3 cycles (12 x register)
- L2 latency = 12 cycles (4 x L1, 48 x register)
- L3 latency = 38 cycles (3 x L2, 12 x L1, 144 x register)
- MM Latency= 195 cycles (5 x L3, 15 x L2, 60 x L1, 720 x register) = 65 ns on a 3 GHz CPU